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The following code results in a combinational logic warning but I don't see it. Perhaps someone here can explain.

process(clk_count_400hz)
begin
    if (clk_count_400hz <= x"002710") then
        clk_count_400hz <= clk_count_400hz + 1;
        clk_400hz_enable <= '0';
    else
        clk_count_400hz <= x"000000";
        clk_400hz_enable <= '1';
    end if;
end process;

I've tried rewriting it in multiple ways but still get the same warning. It seems clk_count_400hz should simply count up and then the register reset back to 0 when x"002710" is exceeded.

The following code results in a combinational logic warning but I don't see it. Perhaps someone here can explain.

process(clk_count_400hz)
begin
    if (clk_count_400hz <= x"002710") then
        clk_count_400hz <= clk_count_400hz + 1;
        clk_400hz_enable <= '0';
    else
        clk_count_400hz <= x"000000";
        clk_400hz_enable <= '1';
    end if;
end process;

I've tried rewriting it in multiple ways but still get the same warning. It seems clk_count_400hz should simply count up and then the register reset back to 0 when x"002710" is exceeded.

• vhdl

Share Improve this question Follow edited Nov 16, 2024 at 16:36 mkrieger1 23.6k77 gold badges6464 silver badges8282 bronze badges asked Nov 16, 2024 at 6:42 treecatttreecatt 2111 silver badge11 bronze badge 4

• In VHDL it is used both ways depending on the context as shown. It is a comparison operator in an IF-THEN-ELSE statement or an assignment operator. In any case, I have solved that issue but have one remaining issue that isn't making any sense. – treecatt Commented Nov 16, 2024 at 8:07
• Can you include what "combinational warning" you get? – mkrieger1 Commented Nov 16, 2024 at 16:38
• Provide a minimal reproducible example with the complete warning message. It would be from a synthesis tool that doesn't accept the description as sequential RTL logic from the lack of evaluation of a clock edge. In synthesis with at least one element of clk_count_400hz inverted by an increment will cause feedback and oscillation. If you had simulated first you might have run into a delta cycle limit for a particular simulator implementation without the passage of simulation time driven by evaluating a periodic clock edge. It would otherwise not be functional, a good hint you should simulate before synthesis. – user16145658 Commented Nov 16, 2024 at 20:46
• This line of code clk_count_400hz <= clk_count_400hz + 1; is feedback around combinational logic, which is really bad for synthesis workflows. Put it in a synchronous process to correctly model a synchronous counter. If you don't know why 'feedback around combinational logic' is bad search the term or search 'how to avoid creating latches in your fpga'. – Mikef Commented Nov 17, 2024 at 1:18

Add a comment  | 

1 Answer 1

Sorted by: Reset to default 3

Combinational logic feedback happens when a circuit triggers itself - or is its own input. The simplest form of this is:

Y <= not Y ;

Or add the complexity of a process and it becomes:

process (Y)
begin
  Y <= not Y ; 
end process ;

Your process is nothing more than a more complicated form the following:

process (clk_count_400hz)
begin
  clk_count_400hz <= clk_count_400hz + 1 ; 
end process ;

This process updates once every delta cycle. There is no good hardware that does this.

Generally hardware is going to update a counter once every clock. This is coded like:

process (clk)
begin
  if rising_edge(Clk) then 
    clk_count_400hz <= clk_count_400hz + 1 ; 
  end if ; 
end process ;

Applying this to your code, you would have something like:

process(clk)
begin
  if rising_edge(Clk) then 
    if (clk_count_400hz <= x"002710") then
        clk_count_400hz <= clk_count_400hz + 1;
        clk_400hz_enable <= '0';
    else
        clk_count_400hz <= x"000000";
        clk_400hz_enable <= '1';
    end if;
  end if;
end process;

The next question you have to solve is how do these objects get their initial value? On technologies that load behavior at powerup (like Xilinx or Altera), you can initialize the signals, however, for static devices (like ASICs, many plds, and Microchip/Actel) a reset signal is required with the flip-flop.

The following code results in a combinational logic warning but I don't see it. Perhaps someone here can explain.

process(clk_count_400hz)
begin
    if (clk_count_400hz <= x"002710") then
        clk_count_400hz <= clk_count_400hz + 1;
        clk_400hz_enable <= '0';
    else
        clk_count_400hz <= x"000000";
        clk_400hz_enable <= '1';
    end if;
end process;

I've tried rewriting it in multiple ways but still get the same warning. It seems clk_count_400hz should simply count up and then the register reset back to 0 when x"002710" is exceeded.

The following code results in a combinational logic warning but I don't see it. Perhaps someone here can explain.

process(clk_count_400hz)
begin
    if (clk_count_400hz <= x"002710") then
        clk_count_400hz <= clk_count_400hz + 1;
        clk_400hz_enable <= '0';
    else
        clk_count_400hz <= x"000000";
        clk_400hz_enable <= '1';
    end if;
end process;

I've tried rewriting it in multiple ways but still get the same warning. It seems clk_count_400hz should simply count up and then the register reset back to 0 when x"002710" is exceeded.

• vhdl

Share Improve this question Follow edited Nov 16, 2024 at 16:36 mkrieger1 23.6k77 gold badges6464 silver badges8282 bronze badges asked Nov 16, 2024 at 6:42 treecatttreecatt 2111 silver badge11 bronze badge 4

• In VHDL it is used both ways depending on the context as shown. It is a comparison operator in an IF-THEN-ELSE statement or an assignment operator. In any case, I have solved that issue but have one remaining issue that isn't making any sense. – treecatt Commented Nov 16, 2024 at 8:07
• Can you include what "combinational warning" you get? – mkrieger1 Commented Nov 16, 2024 at 16:38
• Provide a minimal reproducible example with the complete warning message. It would be from a synthesis tool that doesn't accept the description as sequential RTL logic from the lack of evaluation of a clock edge. In synthesis with at least one element of clk_count_400hz inverted by an increment will cause feedback and oscillation. If you had simulated first you might have run into a delta cycle limit for a particular simulator implementation without the passage of simulation time driven by evaluating a periodic clock edge. It would otherwise not be functional, a good hint you should simulate before synthesis. – user16145658 Commented Nov 16, 2024 at 20:46
• This line of code clk_count_400hz <= clk_count_400hz + 1; is feedback around combinational logic, which is really bad for synthesis workflows. Put it in a synchronous process to correctly model a synchronous counter. If you don't know why 'feedback around combinational logic' is bad search the term or search 'how to avoid creating latches in your fpga'. – Mikef Commented Nov 17, 2024 at 1:18

Add a comment  | 

1 Answer 1

Sorted by: Reset to default 3

Combinational logic feedback happens when a circuit triggers itself - or is its own input. The simplest form of this is:

Y <= not Y ;

Or add the complexity of a process and it becomes:

process (Y)
begin
  Y <= not Y ; 
end process ;

Your process is nothing more than a more complicated form the following:

process (clk_count_400hz)
begin
  clk_count_400hz <= clk_count_400hz + 1 ; 
end process ;

This process updates once every delta cycle. There is no good hardware that does this.

Generally hardware is going to update a counter once every clock. This is coded like:

process (clk)
begin
  if rising_edge(Clk) then 
    clk_count_400hz <= clk_count_400hz + 1 ; 
  end if ; 
end process ;

Applying this to your code, you would have something like:

process(clk)
begin
  if rising_edge(Clk) then 
    if (clk_count_400hz <= x"002710") then
        clk_count_400hz <= clk_count_400hz + 1;
        clk_400hz_enable <= '0';
    else
        clk_count_400hz <= x"000000";
        clk_400hz_enable <= '1';
    end if;
  end if;
end process;

The next question you have to solve is how do these objects get their initial value? On technologies that load behavior at powerup (like Xilinx or Altera), you can initialize the signals, however, for static devices (like ASICs, many plds, and Microchip/Actel) a reset signal is required with the flip-flop.

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